1. Field of the Invention
The present invention relates to thin film magnetic memory devices, and more particularly to a thin film magnetic memory device provided with memory cells having magnetic tunnel junctions (MTJ).
2. Description of the Background Art
A magnetic random access memory (MRAM) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit, and permits random access to the respective thin film magnetic element.
FIG. 12 is a conceptual diagram illustrating a principle of storing data in a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as the “MTJ memory cell”).
Referring to FIG. 12, the MTJ memory cell includes a tunneling magneto-resistance element TMR having a magneto-resistive (MR) effect with which electric resistance of a material changes according to a magnetization direction of a magnetic element. Tunneling magneto-resistance element TMR is known to exhibit a remarkable MR effect even at room temperature and have a high MR ratio (electric resistance ratio corresponding to the magnetization direction).
Tunneling magneto-resistance element TMR includes ferromagnetic films 201, 202 and an insulating film (tunneling film) 203. In tunneling magneto-resistance element TMR, an amount of tunneling current flowing through insulating film 203 sandwiched between ferromagnetic films 201 and 202 changes according to the direction of electron spins which is determined by the magnetization directions of ferromagnetic films 201 and 202. The number of states that the spinning electrons within ferromagnetic films 201, 202 can take differs depending on the magnetization directions. The tunneling current increases when ferromagnetic films 201 and 202 have the same magnetization directions, while it decreases when the two films have opposite magnetization directions from each other.
Utilizing this phenomenon, tunneling magneto-resistance element TMR can be used as a memory cell storing data of one bit, when the magnetization direction of ferromagnetic film 202 is changed in accordance with stored data while the magnetization direction of ferromagnetic film 201 is fixed, e.g., by an antiferromagnetic material, and the amount of tunneling current flowing through tunneling film 203, i.e., the electric resistance of tunneling magneto-resistance element TMR, is detected. In general, such a tunneling magneto-resistance element is also called a “spin valve”.
Hereinafter, ferromagnetic film 201 having a fixed magnetization direction is also referred to as the “fixed magnetic layer”, and ferromagnetic film 202 having a magnetization direction corresponding to stored data is also referred to as the “free magnetic layer”.
In order to implement a high-density memory device, it is preferable to arrange MTJ memory cells formed of tunneling magneto-resistance elements TMR as described above in a two dimensional array. Generally, a ferromagnetic material has a direction in which it is easier to magnetize (requiring smaller energy for magnetization) according to its crystal structure, shape and others. This direction is commonly called an “easy axis (EA)” direction, and the magnetization direction of free magnetic layer 202 corresponding to stored data is set to the direction along the easy axis. A direction in which the ferromagnetic material is harder to magnetize (requiring greater energy for magnetization) is called a “hard axis (HA)” direction.
FIG. 13 is a conceptual diagram illustrating a data write magnetic field which is applied to an MTJ memory cell in a data write operation.
Referring to FIG. 13, the horizontal axis represents a data write magnetic field H (EA) along the easy axis direction. The vertical axis represents a data write magnetic field H (HA) along the hard axis direction. When the vector sum of data write magnetic fields H (EA) and H (HA) reaches an area outside the asteroid curve 205, the magnetization direction of tunneling magneto-resistance element TMR (i.e., magnetization direction of free magnetic film 202) is rewritten to a direction along the easy axis.
On the contrary, when the data write magnetic field within the area of asteroid curve 205 is being applied, the magnetization direction of tunneling magneto-resistance element TMR is not updated, and the stored content is held in a non-volatile manner.
As shown in FIG. 13, data write magnetic field H (EA) required for data rewriting is reduced when data write magnetic field H (HA) is applied at the same time. In other words, the operating points 206 and 207 at the data writing are represented by vector sums of data write magnetic field H (HA) of a fixed direction irrelevant to a level of write data and data write magnetic field H (EA) of a variable direction corresponding to the write data. Further, data write magnetic fields H (HA) and H (EA) at the operating points 206, 207 are designed such that they do not reach the area outside asteroid curve 205 alone.
FIG. 14 is a conceptual diagram illustrating arrangement of data write interconnections in a memory cell array formed of MTJ memory cells.
Referring to FIG. 14, in the memory cell array having tunneling magneto-resistance elements TMR constituting respective MTJ memory cells arranged in rows and columns, data write interconnections 210 and 215 are arranged in a matrix. Data write interconnections 210 and 215 are provided with data write currents for generation of one and the other of data write magnetic fields H (EA) and H (HA), respectively.
For example, assume that data write magnetic field H (HA) is generated by data write interconnections 210 and data write magnetic field H (EA) is generated by data write interconnections 215. In this case, a data write current having a fixed direction is selectively passed through data write interconnections 210, and a data write current having a direction corresponding to write data is selectively passed through data write interconnections 215. An MTJ memory cell designated as a data write target receives the data write currents from both data write interconnections 210 and 215 corresponding thereto.
As a result, selective data write to a plurality of tunneling magneto-resistance elements TMR arranged in two dimensions becomes possible by controlling the data write current supply to data write interconnections 210 and 215 in accordance with address selection.
FIG. 15 is a conceptual diagram illustrating a configuration for reading data from an MTJ memory cell.
Such a configuration is disclosed in technical documents including “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000, and “A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7.6, February 2001.
Referring to FIG. 15, as described above, data write to an MTJ memory cell, or tunneling magneto-resistance element TMR, is carried out utilizing a magnetic field generated by data write currents flowing through a digit line DL and a bit line BL. For example, digit line DL corresponds to data write interconnection 210 shown in FIG. 14, and bit line BL corresponds to data write interconnection 215.
An access transistor ATR is provided as an access element for carrying out the data read from tunneling magneto-resistance element TMR, which turns on or off in accordance with a voltage on a word line WL. A metal oxide semiconductor (MOS) transistor is typically employed as access transistor ATR. One of source/drain regions of access transistor ATR is electrically coupled to tunneling magneto-resistance element TMR, and the other of source/drain regions is coupled to a fixed voltage such as a ground voltage.
On the data read, word line WL is activated to turn on access transistor ATR, while bit line BL is set to a voltage different from the relevant fixed voltage. Accordingly, a current corresponding to the magnetization direction of tunneling magneto-resistance element TMR, or the stored data, passes via access transistor ATR through a current path including bit line BL and tunneling magneto-resistance element TMR.
Thus, by comparing the bit line current at this time with a reference current, the magnetization direction of tunneling magneto-resistance element TMR, or the stored data in the MTJ memory cell, can be determined. Since the bit line current at the time of data read is considerably small compared to the data write current, the magnetization direction of tunneling magneto-resistance element TMR would not vary due to the current flowing during the data read. This permits non-destructive data read.
An MRAM device is provided with a memory array having such MTJ memory cells collectively arranged in rows and columns. The data read operation is performed on a “selected memory cell” designated as a data read target from within the memory array.
FIG. 16 is a circuit diagram showing a configuration for reading data from a memory array formed of MTJ memory cells.
Referring to FIG. 16, the memory array includes a plurality of MTJ memory cells MC arranged in n rows and m columns (n and m are natural numbers) and a plurality of reference cells RMC. The plurality of reference cells RMC are arranged in a column direction to form a reference cell column 11. As described above, each MTJ memory cell MC has two types of electric resistances in accordance with stored data. Hereinafter, the two types of electric resistances are expressed as Rmax and Rmin (Rmax>Rmin). Each reference cell RMC is designed to have an electric resistance of an intermediate level between Rmax and Rmin.
Word lines WL1-WLn are provided for selecting rows of MTJ memory cells (hereinafter, also simply referred to as “memory cell rows”) in a data read operation. Digit lines DL1-DLn are provided for selecting the memory cell rows in a data write operation. Each word line and each digit line are shared by MTJ memory cells MC and reference cell RMC belonging to the same memory cell row.
Bit lines BL1-BLm are provided corresponding to respective columns of MTJ memory cells Hereinafter, also simply referred to as “memory cell columns”). A reference bit line BLr is provided corresponding to reference cell column 11. Selection of the memory cell columns and reference cell column is carried out using column select signals CS1-CSm, CSr.
MTJ memory cells MC each have a tunneling magneto-resistance element TMR and an access transistor ATR that are connected in series between corresponding one of bit lines BL1-BLm and a ground voltage GND. Access transistor ATR has a gate connected to corresponding one of word lines WL1-WLn.
Each reference cell RMC has a reference resistance element TMRr and an access transistor ATRr that are connected in series between reference bit line BLr and ground voltage GND. As the access transistors ATR, ATRr, a metal oxide semiconductor (MOS) transistor being a field effect transistor formed on a semiconductor substrate, in particular an N channel MOS transistor, is typically employed.
Column select gates CSG1-CSGm are provided between bit lines BL1-BLm and a data line DSL. A column select gate CSGr is connected between reference data line DSLr and reference bit line BLr. Column select gates CSG1-CSGm turn on/off in response to column select signals CS1-CSm, and column select gate CSGr turns on/off in response to column select signal CSr.
In the data read operation, the word line of a selected row is activated to a high level (hereinafter, “H level”), and the word lines of the remaining, non-selected rows are inactivated to a low level (hereinafter, “L level”). Further, the column select signal of a selected column is activated to an H level, and column select signal CSr is activated to an H level regardless of a result of address selection.
In response, access transistors ATR and ATRr belonging to the selected row turn on, and the bit line of the selected column (hereinafter, “selected bit line”) having been pulled down to ground voltage GND via a selected memory cell is connected to a data reading sense amplifier 50 via data line DSL. Similarly, reference bit line BLr pulled down to ground voltage GND via a reference cell belonging to the memory cell row including the selected memory cell is connected via reference data line DSLr to data reading sense amplifier 50.
In this state, data line DSL and reference data line DSLr are pulled up with a common voltage. As a result, a memory cell current Icell in accordance with the electric resistance (or, the stored data) of the selected memory cell occurs on a current path including the selected memory cell, selected bit line and data line DSL. Memory cell current Icell has one of two types of levels in response to the stored data in the selected memory cell. A reference current Iref of a level corresponding to the middle of the two types of levels of the memory cell current occurs on a current path including the reference cell, reference data line DSLr and reference bit line BLr.
Thus, it is possible to generate read data RDT reflecting the stored data of the selected memory by detecting and amplifying a current difference between memory cell current Icell and reference current Iref by sense amplifier 50.
As described above, for the data read in the MRAM device, it is necessary to design memory cell current Icell and reference current Iref passing through a selected bit line and the reference bit line, respectively, such that they accurately reflect the electric resistances of a selected memory cell and the reference cell.
A bit line of a selected column through which the memory cell current Icell flows is connected not only with the selected memory cell but also with a plurality of non-selected memory cells belonging to the same memory cell row. In the non-selected memory cells, access transistors ATR are turned off in response to inactivation of the corresponding word lines.
However, an off leakage current occurs even in the access transistors that should be turned off, due to a sub-threshold current and a diffused leakage current from a diffusion region. Since the off leakage current also constitutes the current passing through the selected bit line, an increase of the off leakage current would cause a problem that memory cell current Icell does not necessarily represent the accurate electric resistance of the selected memory cell, leading to degradation of data read margin. The same applies to the access transistor ATRr of the reference cell.
Particularly, in order to form a system LSI (Large Scale Integrated circuit), in a configuration where the MRAM device and a logic unit are mounted on the same chip, a MOS transistor having a relatively small threshold voltage is employed in the logic unit for a high speed operation. With such a MOS transistor, although such a high speed operation may be expected as the operating current upon turning on is large, the off leakage current would also become when turning on.
If the MOS transistor used in the logic unit is also employed as the access transistor of the MTJ memory cell, the data read margin will decrease in the MRAM device due to an influence of the off leakage current, thereby hindering stabilization of the circuit operation.